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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 11. Indirect Address Example
PREAMBLE, 32-BIT
ALL ONES
ST
00
OP PHYADDR
00 0_0000
DTYPE
0_0100
TA
ADDRESS/DATA
0000_1111_0000_0001
ST OP PHYADDR
00 10 0_0000
DTYPE
0_0100
TA
ADDRESS/DATA
0000_1010_0101_1111
PREAMBLE, 32-BIT
REGISTER ADDRESS
OP = READ
DATA RETURNED
ALL ONES
TO BE ACCESSED
OP = ADDRESS
DEVICE TYPE = XGXS
DEVICE TYPE = XGXS
Table 8 shows PHY XGXS registers as described in IEEE Draft P802.3ae. The shaded areas are used to indicate
register addresses that are speci ? ed in the draft but are not used in this implementation.
There are two vendor supported register ranges. The 4.8000h register range is used for accessing and program-
ming the XGXS registers implemented in the programmable array of the ORT82G5 (XGXS and packet genera-
tor/checker registers). All corresponding registers are listed in Table 7. All ORT82G5 embedded core registers can
be accessed through the 4.9xxxh registers shown in Table 8, where the address is directly mapped to the
ORT82G5 embedded registers. Refer to the ORT82G5 data sheet for complete details on the ORT82G5 embed-
ded core register memory map and register de ? nitions.
Register Descriptions
Table 7. Register Map for XGXS IP (Device Address = 4)
Table 8. XGXS Registers
Register Address
0
1
2, 3
4
5
6 - 23
24
25 - 32767
32768 - 65535
Register Name
PHY XGXS Control 1
PHY XGXS Status 1
PHY XGXS Identi ? er
Reserved
PHY XGXS Status 2
Reserved
10G PHY XGXS Lane status
Reserved
Vendor speci ? c (TBD)
Bit(s)
Name
Description
R/W
Reset Value
Control 1 Registers
4.0.15
Reset
1 = PHY XA reset, 0 = Normal operation
R/W S/C
0
1 = Enable Loop back, 0 = Disable Loop back
Writing to this bit sets the corresponding ORT82G5
4.0.14
Loop Back
register bits:
R/W
0
CH A = 30801 [0,1,2,3]
CH B = 30901 [0,1,2,3]
4.0.13
Speed Selection
Value always 0
R
0
4.0.12
Reserved
Value always 0
R
0
17
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